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Akihiko Odaki authored
riscv_trigger_init() had been called on reset events that can happen several times for a CPU and it allocated timers for itrigger. If old timers were present, they were simply overwritten by the new timers, resulting in a memory leak. Divide riscv_trigger_init() into two functions, namely riscv_trigger_realize() and riscv_trigger_reset() and call them in appropriate timing. The timer allocation will happen only once for a CPU in riscv_trigger_realize(). Fixes: 5a4ae64c ("target/riscv: Add itrigger support when icount is enabled") Signed-off-by:
Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by:
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>Akihiko Odaki authoredriscv_trigger_init() had been called on reset events that can happen several times for a CPU and it allocated timers for itrigger. If old timers were present, they were simply overwritten by the new timers, resulting in a memory leak. Divide riscv_trigger_init() into two functions, namely riscv_trigger_realize() and riscv_trigger_reset() and call them in appropriate timing. The timer allocation will happen only once for a CPU in riscv_trigger_realize(). Fixes: 5a4ae64c ("target/riscv: Add itrigger support when icount is enabled") Signed-off-by:
Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by:
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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