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    7ca96e1a
    target/mips: Fix minor bug in FPU · 7ca96e1a
    Mateja Marjanovic authored
    
    
    Wrong type of NaN was generated for IEEE 754-2008 by MADDF.<D|S> and
    MSUBF.<D|S> instructions when the arguments were (Inf, Zero, NaN) or
    (Zero, Inf, NaN).
    
    The if-else statement establishes if the system conforms to IEEE
    754-1985 or IEEE 754-2008, and defines different behaviors depending
    on that. In case of IEEE 754-2008, in mentioned cases of inputs,
    <MADDF|MSUBF>.<D|S> returns the input value 'c' [2] (page 53) and
    raises floating point exception 'Invalid Operation' [1] (pages 349,
    350).
    
    These scenarios were tested and the results in QEMU emulation match
    the results obtained on the machine that has a MIPS64R6 CPU.
    
    [1] MIPS Architecture for Programmers Volume II-a: The MIPS64
        Instruction Set Reference Manual, Revision 6.06
    [2] MIPS Architecture for Programmers Volume IV-j: The MIPS64
        SIMD Architecture Module, Revision 1.12
    
    Signed-off-by: default avatarMateja Marjanovic <mateja.marjanovic@rt-rk.com>
    Message-Id: <1553008916-15274-2-git-send-email-mateja.marjanovic@rt-rk.com>
    Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
    [AJB: fixed up commit message]
    Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
    7ca96e1a
    target/mips: Fix minor bug in FPU
    Mateja Marjanovic authored
    
    
    Wrong type of NaN was generated for IEEE 754-2008 by MADDF.<D|S> and
    MSUBF.<D|S> instructions when the arguments were (Inf, Zero, NaN) or
    (Zero, Inf, NaN).
    
    The if-else statement establishes if the system conforms to IEEE
    754-1985 or IEEE 754-2008, and defines different behaviors depending
    on that. In case of IEEE 754-2008, in mentioned cases of inputs,
    <MADDF|MSUBF>.<D|S> returns the input value 'c' [2] (page 53) and
    raises floating point exception 'Invalid Operation' [1] (pages 349,
    350).
    
    These scenarios were tested and the results in QEMU emulation match
    the results obtained on the machine that has a MIPS64R6 CPU.
    
    [1] MIPS Architecture for Programmers Volume II-a: The MIPS64
        Instruction Set Reference Manual, Revision 6.06
    [2] MIPS Architecture for Programmers Volume IV-j: The MIPS64
        SIMD Architecture Module, Revision 1.12
    
    Signed-off-by: default avatarMateja Marjanovic <mateja.marjanovic@rt-rk.com>
    Message-Id: <1553008916-15274-2-git-send-email-mateja.marjanovic@rt-rk.com>
    Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
    [AJB: fixed up commit message]
    Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
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