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Sai Pavan Boddu authored
The GICv2 allows the implementation to implement a variable number of priority bits; unimplemented bits in the priority registers are read as zeros, writes ignored. We were previously always implementing a full 8 bits of priority, which is allowed but not what the real hardware typically does (which is usually to have 4 or 5 bits of priority). Add a new device property to allow the number of implemented property bits to be specified. Signed-off-by:
Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by:
Peter Maydell <peter.maydell@linaro.org>
Reviewed-by:
Peter Maydell <peter.maydell@linaro.org>
[PMM: improved commit message]
Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>Sai Pavan Boddu authoredThe GICv2 allows the implementation to implement a variable number of priority bits; unimplemented bits in the priority registers are read as zeros, writes ignored. We were previously always implementing a full 8 bits of priority, which is allowed but not what the real hardware typically does (which is usually to have 4 or 5 bits of priority). Add a new device property to allow the number of implemented property bits to be specified. Signed-off-by:
Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by:
Peter Maydell <peter.maydell@linaro.org>
Reviewed-by:
Peter Maydell <peter.maydell@linaro.org>
[PMM: improved commit message]
Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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