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Anup Patel authored
We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by:
Anup Patel <anup.patel@wdc.com>
Signed-off-by:
Anup Patel <anup@brainfault.org>
Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
Reviewed-by:
Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>Anup Patel authoredWe add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by:
Anup Patel <anup.patel@wdc.com>
Signed-off-by:
Anup Patel <anup@brainfault.org>
Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
Reviewed-by:
Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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