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Peter Maydell authored
target-arm queue: * Clean up handling of bad mode switches writing to CPSR, and implement the ARMv8 requirement that they set PSTATE.IL * Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps on perf monitor register accesses * Don't implement stellaris-pl061-only registers on generic-pl061 * Fix SD card handling for raspi * Add missing include files to MAINTAINERS * Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW * Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF # gpg: Signature made Fri 26 Feb 2016 15:19:07 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160226: target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW sdhci: add quirk property for card insert interrupt status on Raspberry Pi sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts" MAINTAINERS: Add some missing ARM related header files raspi: fix SD card with recent sdhci changes ARM: PL061: Checking register r/w accesses to reserved area target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps target-arm: Fix handling of SDCR for 32-bit code target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 target-arm: Make mode switches from Hyp via CPS and MRS illegal target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL target-arm: Forbid mode switch to Mon from Secure EL1 target-arm: Add Hyp mode checks to bad_mode_switch() target-arm: Add comment about not implementing NSACR.RFR target-arm: In cpsr_write() ignore mode switches from User mode linux-user: Use restrictive mask when calling cpsr_write() target-arm: Raw CPSR writes should skip checks and bank switching target-arm: Add write_type argument to cpsr_write() target-arm: Give CPSR setting on 32-bit exception return its own helper Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>Peter Maydell authoredtarget-arm queue: * Clean up handling of bad mode switches writing to CPSR, and implement the ARMv8 requirement that they set PSTATE.IL * Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps on perf monitor register accesses * Don't implement stellaris-pl061-only registers on generic-pl061 * Fix SD card handling for raspi * Add missing include files to MAINTAINERS * Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW * Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF # gpg: Signature made Fri 26 Feb 2016 15:19:07 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160226: target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW sdhci: add quirk property for card insert interrupt status on Raspberry Pi sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts" MAINTAINERS: Add some missing ARM related header files raspi: fix SD card with recent sdhci changes ARM: PL061: Checking register r/w accesses to reserved area target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps target-arm: Fix handling of SDCR for 32-bit code target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 target-arm: Make mode switches from Hyp via CPS and MRS illegal target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL target-arm: Forbid mode switch to Mon from Secure EL1 target-arm: Add Hyp mode checks to bad_mode_switch() target-arm: Add comment about not implementing NSACR.RFR target-arm: In cpsr_write() ignore mode switches from User mode linux-user: Use restrictive mask when calling cpsr_write() target-arm: Raw CPSR writes should skip checks and bank switching target-arm: Add write_type argument to cpsr_write() target-arm: Give CPSR setting on 32-bit exception return its own helper Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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