Commits · main · Anton / hexagon-insn-bench

Dec 16, 2022
- Emit `vcombine` for vector reg pair · a3474192
  Anton authored Dec 16, 2022
  
  a3474192
- Replace `is_reg_32` with `get_reg_width` to instead get the width · 863b7ad0
  Anton authored Dec 16, 2022
  
  863b7ad0
- Add `-mhvx` flag to compile command · 4c58900f
  Anton authored Dec 16, 2022
  
  4c58900f
Dec 02, 2022
- Handle single register HVX instructions · 13575d99
  Anton authored Dec 02, 2022
  
  13575d99
Oct 19, 2022
- Add readme · 982cf598
  Anton authored Oct 19, 2022
  
  982cf598
- Add `xlabel` for 3rd plot · debf223e
  Anton authored Oct 19, 2022
  
  debf223e
- Use `realpath` for abs. paths + path error checking · 41d20caa
  Anton authored Oct 19, 2022
  
  41d20caa
- Move `allocframe` from loop prologue · 8d0c9364
  Anton authored Oct 19, 2022
  
  8d0c9364
- Fix missed `paths -> qemus` renaming · b1a86d05
  Anton authored Oct 19, 2022
  
  b1a86d05
- Add error check for args · 038fa7d3
  Anton authored Oct 19, 2022
  
  038fa7d3
- Fix comment · 7ec66a37
  Anton authored Oct 19, 2022
  
  7ec66a37
- Cleanup and add more comments · 11c9edd6
  Anton authored Oct 19, 2022
  
  11c9edd6
- Pushing cleaned-up version of project to its new home · c7afe262
  Anton authored Oct 19, 2022
  
  c7afe262